Generally, in integrated circuits, a soft-fail (or soft-failure) may be described as a minor defect in an electrical connection. The defect in the electrical connection may lead to an increase in electrical resistance through the electrical connection. Typically, the defect may result in an increase in the electrical resistance on the order of a few times to several thousand times the electrical resistance of a defect-free electrical connection.
The increase in the electrical resistance of the electrical connection may introduce additional delay to a signal propagation path containing the electrical connection. FIG. 1a illustrates two electrical signal paths, a first path 105 labeled “NORMAL” and a second path 110 labeled “HI-R.” Both electrical signal paths are connected to a signal input labeled “IN.” Both first path 105 and second path 110 comprise two signal vias, with one of the two vias in second path 110 being faulty (shown with cross hatching and crossed out). The faulty via in second path 110 may have a higher electrical resistance than the other vias shown.
FIG. 1b illustrates three signal traces, a first trace 155 representing an input signal, a second trace 160 representing an electrical signal measured at an output of first path 105, and a third trace 165 representing an electrical signal measured at an output of second path 110. Both second trace 160 and third trace 165 arise from the input signal (first trace 155) that transition from a low electric potential to a high electric potential.
Due to an inherent electrical resistance of signal vias, an electrical signal propagating through first path 105 will experience a small propagation delay. However, the propagation delay is negligible. A rise time of the input signal propagating through first path 105 (shown as interval 175) may be substantially equal to a rise time of the input signal (shown as interval 170).
However, due to a significant increase in electrical resistance of second path 110 due to the faulty via, a rise time of the input signal propagating through second path 110 (shown as interval 180) may be substantially greater than a rise time of the input signal (shown as interval 170). Duration of interval 180 may be a function of the increase in electrical resistance due to the faulty via, with a greater increase in electrical resistance resulting in a greater duration of interval 180.
The increase in propagation delay due to a soft-fail may be difficult to detect using standard circuit testing techniques. Additionally, the soft-fails that are detectable tend to be soft-fails that increase the electrical resistance by a substantial margin, i.e., soft-fail that marginally increase the electrical resistance by only a few hundred times may not be detectable.
FIG. 2 illustrates a data plot of a distribution of propagation delay increases due to soft-fails. As shown in FIG. 2, propagation delay increases of less than 1 ns may be considered to be within standard manufacturing tolerances and may be acceptable, while propagation delay increases of more than 3 ns may be detectable by standard circuit testing techniques. However, a relatively small number of soft-fails result in a propagation delay increase of 3 ns or more.
Soft-fails that cause a propagation delay increase of between 1 ns and 3 ns may make up a significant number of soft fails. However, standard circuit testing techniques may not be able to detect propagation delay increases between 1 ns and 3 ns. Therefore, there is a need for circuit testing techniques capable of detecting small propagation delay increases.